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IDE/CF Driver
11-2-1 ATA (TRUE IDE) COMMUNICATION
The interface between an ATA device and host is comprised of data bus, address bus and
various control signals, as shown in Figure 11-2. Three forms of data transfer are possible,
each with several timing modes:
1
PIO (programmed input/output). PIO must always be possible; indeed, it may be the
only possible transfer form on certain hardware. Using PIO, data requests are satisfied
by direct reads or writes to the DATA register. The IDENTIFY_DEVICE command and
standard sector and multiple sector read/write commands always involve this type of
transfer. Five timing modes (0, 1, 2, 3 and 4) are standard; two more (5 and 6) are
defined in the CF specification.
2
Mutiword DMA. In Multiword DMA mode, a DMARQ and –DMACK handshake initiates
automatic data transmission, during which the host moves data between its memory
and the bus. The DMA read/write commands ( READ_DMA , WRITE_DMA ) may use
Multiword DMA. Three timing modes (0, 1 and 2) are standard; two more (3 and 4) are
defined in the CF specification.
3
Ultra DMA. The purposes of several control signals are reassigned during Ultra DMA
transfers. For example, IORDY becomes either DDMARDY or DSTROBE (depending on
the direction) to control data flow. The DMA read/write commands ( READ_DMA ,
WRITE_DMA ) may use Ultra DMA. Seven timing modes (0, 1, 2, 3, 4, 5 and 6) are
standard.
MCU/MPU
D[0..15]
A[0..2]
-CS0
-CS1
-IORD
-IOWR
-IORDY
INTRQ
-RESET
DMARQ
-DMACK
-DASP
-CD1
-CD2
IDE Drive / CF Card
D00..D15
A00..A02
-CS0
-CS1
-IORD
-IOWR
-IORDY
INTRQ
-RESET
DMARQ
-DMACK
-DASP
-CD1
-CD2
-CSEL
-ATA_SEL
Figure 11-2 True IDE (ATA) host/device connection
128
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